----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Antti Lukats 
-- 
-- Create Date:    12:11:29 09/06/2007 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name:   Xiltendo
-- Target Devices: XC9572XL
-- Tool versions:  ISE 9.1+
--
-- 
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity top is Port ( 
	-- Cart Slot
	PHI	: in  STD_LOGIC; -- Clock input 4.19 / 8.38 / 16.76
	CS   	: in  STD_LOGIC; -- ROM space Chip Select
	RD   	: in  STD_LOGIC; -- Read
	WR   	: in  STD_LOGIC; -- Write
	REQ  	: out STD_LOGIC; -- IRQ/DRQ output
	AD   	: inout  STD_LOGIC_VECTOR (7 downto 0) -- 8 bit of AD bus only !
	);
end top;

architecture Behavioral of top is

signal CNT: STD_LOGIC_VECTOR (7 downto 0);

begin
	process (WR)
	begin
		if (rising_edge(WR)) then
			CNT <= CNT + "00000001";
		end if;
	end process;

	AD <= CNT when CS='0' and RD='0' else "ZZZZZZZZ";
        
end Behavioral;

